ASIC Verification Engineer Job Description
ASIC Verification Engineer Duties & Responsibilities
To write an effective ASIC verification engineer job description, begin by listing detailed duties, responsibilities and expectations. We have included ASIC verification engineer job description templates that you can modify and use.
Sample responsibilities for this position include:
ASIC Verification Engineer Qualifications
Qualifications for a job description may include education, certification, and experience.
Education for ASIC Verification Engineer
Typically a job would require a certain level of education.
Employers hiring for the ASIC verification engineer job most commonly would prefer for their future employee to have a relevant degree such as Master's and Bachelor's Degree in Computer Engineering, Electrical Engineering, Computer Science, Engineering, Communications, Science, Education, Graduate, Communication, Design
Skills for ASIC Verification Engineer
Desired skills for ASIC verification engineer include:
Desired experience for ASIC verification engineer includes:
ASIC Verification Engineer Examples
ASIC Verification Engineer Job Description
- Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
- Self-checking/random, reusable, automated verification environment
- Executing constrained random generators and reference models
- Writing and executing test plans for IP and subsystem SOC level verification
- Working with architects and project leads on verification requirements, metrics
- Working with IP and SOC architects to provide configuration/design for APU SOCs
- Working with Emulation and silicon platform team to clear/debug issues related to PCIE/Root complex
- You will be involved in the definition and management of appropriate verification specifications, processes and routines, helping to ensure they are up-to-date and fit for purpose, liaising very closely with representatives of the ASIC organisation in key sites globally
- You will contribute to the development and improvement of documentation relating to the ASIC simulation and verification specifications and related processes
- You will contribute to the technical evolution of the modelling group’s automated test infrastructure, suggesting appropriate technical changes, process improvements or other efficiencies to improve the service offered to users and the value delivered to the business
- Bachelor/Master Degree in Electrical/Computer Engineering
- 5+ years MS/BS
- Demonstrated ability to work independently in a multi-disciplinary group environment
- Broad knowledge with Video techniques, SOC architecture and Computer architecture is a big plus
- BS or MS degree in electrical or computer engineering or closely related degree strongly preferred
- Comfortable in a Unix development environment (make, scripting, SVN)
ASIC Verification Engineer Job Description
- You will be experienced in Python and C++
- You will be proactive and flexible, capable of working in a role where priorities can change frequently
- You will be comfortable working with distributed teams and liaising with other groups within the global WDC organisation
- Be responsile for System Management IP design
- Will be responsible for building UVM testbench for ASIC Block verification
- Will develop testplans & Functional cover points specifications for block DV
- Will develop & execute test cases to achieve Coverage convergence & DV signoff for ASIC blocks
- Performing various types of physical verification checks (such as LVS, DRC
- As a verification Engineer you’ll help design and implement test benches, come up with a test plan, write test cases, run test regressions to help verify designs
- Define, develop, and execute self-checking tests for complex digital ASICs
- Familiarity with debug techniques both inside FPGA logic at the board level
- Familiarity with advanced verification techniques such as object-oriented testbenches and formal verification
- Experience with standard test equipment such as oscilloscopes and logic analyzer
- Data, software, and/or network security
- Experience leading small-to-medium teams of designers and/or verifiers on a common FPGA design
- Contribute to verification and bring-up of networking ASICs/FPGAs being developed
ASIC Verification Engineer Job Description
- Resolving coverage issues using coverage methodologies formal methods
- When applying online, please upload your RESUME and TRANSCRIPT
- Please ensure The filenames of all attachments include your first name, last name and posting number
- Develop coverage models and verification environments using UVM-SystemVerilog / C++
- Develop, enhance, and sustain a UVM based verification environment for ASIC development
- Integrate automotive compliance (ISO26262) safety concepts and safety measures
- Apply standard best practices (constrained random, functional cover group, assertion, methodologies)
- Create firmware driven simulations for ASIC design verification
- Participate in the ASIC design process
- Utilize high-level architectural documentation along with algorithm descriptions to create self-checking and reusable testbenches from scratch
- Write scripts to automate some tasks of the ASIC design/verification process
- Create tools to automate testing of ASICs in the lab
- Looking for an energetic individual with excellent communication skills and eagerness to learn!
- Post-BS degree student working toward an MS in EE or CS
- Experience with any packet based protocols (PCI Express ), Network centric designs (Ethernet, IP, FC)
- Graduate students, electronic engineering and computer science related majors
ASIC Verification Engineer Job Description
- Utilize UVM to create drivers, monitors, predictors, and scoreboards
- Define and Implement the ASIC/SoC verification environment
- Develop block and system-level test benches and verification environments using Verilog/SystemVerilog and C
- Develop support utilities for verification automation, test bench automation, regression and other verification enhancements to improve productivity and functional coverage
- Mentor verification team and provide technical support for verification activities
- Support the development of verification test plans, test suites and verification activities
- Contribute to verification infrastructure development for complex ASICs
- Develop test plans based on functional requirements, applicable standards requirements
- Responsible for the definition, development, and execution of self-checking tests
- Contribute to the post-silicon validation of ASICs in the lab, writing tests and scripts
- Excellent programming skills on C, C++, Verilog, or System Verilog and
- Experience in script programming(Perl/Python/Makefile/Shell and ) would be a plus
- Experience in designing complex digital hardware systems and developing hardware architectures for algorithm implementation would be a plus
- Testbench development for the verification of RTL blocks using VHDL and/or SystemVerilog
- Proficiency using ASIC and/or FPGA simulation and synthesis tools
- Familiarity with best practice chip-level verification techniques and languages
ASIC Verification Engineer Job Description
- Working with simulation environments based on UVM and Google Test and C/C++
- Supporting regression runs
- Expanded domain knowledge and knowledge of products and systems in an assigned area
- Design, test, analyze, integrate, qualify and document hardware of moderate to high complexity such as multiple hardware components or mixed electrical technologies
- This position is for a motivated Senior Electrical or Computer engineering experienced candidate to be involved in the design, implementation, verification and integration of a wide variety of high-performance digital ASICs and FPGAs applied to data concentration and conversion applications
- Debug test failures to determine if it is a design or verification issue
- Provides technical expertise to a project team of pre-silicon VLSI engineers along with development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing
- Reviews and evaluates designs and project activities for compliance with pre-silicon VLSI technology and development guidelines and standards
- Provides pre-silicon VLSI-specific and technical expertise along with the overall architecture design and platform leadership to cross-organization projects, programs, and activities
- Provides leadership of project team of other pre-silicon VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products
- Familiarity with revision control concepts and tools
- Ability to work with minimal supervision, as a part of a team of engineers with a variety of skills and backgrounds, matrixed into projects with aggressive schedules and frequent milestones
- ASIC / FPGA lab validation with advanced lab equipment
- Design for Test (DFT) and manufacturability issues
- Digital circuit architecture, design, resource tradeoffs, timing analysis and timing closure
- 3 years of System Verilog experience in UVM or OVM development environment, and at least 5 years of Digital Test bench development experience