RTL Design Engineer Job Description
RTL Design Engineer Duties & Responsibilities
To write an effective RTL design engineer job description, begin by listing detailed duties, responsibilities and expectations. We have included RTL design engineer job description templates that you can modify and use.
Sample responsibilities for this position include:
RTL Design Engineer Qualifications
Qualifications for a job description may include education, certification, and experience.
Education for RTL Design Engineer
Typically a job would require a certain level of education.
Employers hiring for the RTL design engineer job most commonly would prefer for their future employee to have a relevant degree such as Bachelor's and Master's Degree in Computer Engineering, Electrical Engineering, Computer Science, Design, Engineering, Science, Electronics Engineering, Architecture, Computer, Information Systems
Skills for RTL Design Engineer
Desired skills for RTL design engineer include:
Desired experience for RTL design engineer includes:
RTL Design Engineer Examples
RTL Design Engineer Job Description
- Interacting closely with other teams such as the Applications, Test Engineering and Design Evaluation
- Work with wireless system (platform) team and make sure solution works end-to-end
- Support Design and Verification of Wireless/Bluetooth SoCs or IPs
- Perform RTL design and Verification of digital macros, working from an architectural description
- Run Lint/CDC and other tools to check the quality of the IP/SoC
- Support Validation of the IP/SoC on FPGA platform and support FPGA code development
- Develop micro-architecture, and SystemVerilog RTL to meet size, timing specificationso
- Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, pipelining, FPGA usage
- Developing design, verification and validation tools and flows, as needed
- Work with implementation team to synthesize and place/route the synthesized netlist, also work to analyze timing
- Design knowledge of one/more industry standard bus interfaces (PCIe, SPI, SRIO, USB, XAUI ) and memory interfaces (DDR2, DDR3 etc
- Experience in interfacing with architecture and Physical implementation teams is a plus
- Design knowledge of one/more industry-standard bus interfaces (PCIe, SPI, SRIO, USB, XAUI, ) and memory interfaces (DDR2, DDR3, ) are a plus
- Must be currently enrolled in a BSEE/MSEE program (or equivalent)
- Must have knowledge of computer architecture and logic design
- Must have some experience with Verilog/VHDL and C++
RTL Design Engineer Job Description
- You own CPU micro-architecture specification and design
- You work closely with engineers across performance modeling, validation, and implementation to meet all functional requirements, performance, power and area goals
- Leading, supervising, coaching, and mentoring a small team of RTL & DV engineers
- Micro-architecture of digital blocks and hardware/firmware partitioning
- Digital design and RTL coding, scripting, and automation
- Conducting and subjecting to documentation and code reviews
- Contributing to test plans and calling out design and verification requirements for tracking
- Creating Engineering Change Requests (ECRs) and implementing and verifying Engineering Change Orders (ECOs) on RTL, and on synthesized, pre- and post-route netlists
- Coordinating with leads from other teams such as DFT, analog design, protocol-specific PCS design, I/O controller teams, microcontroller firmware, IP/SOC deployment, front-end design, physical design, post-silicon validation
- Interfacing with internal and external development partners, IP vendors and service providers
- Thorough knowledge of chip architecture
- Understanding of high performance techniques and trade-offs
- 9+ years of experience in RTL and or Verification Background (System Verilog, UVM, and parameterized/configurable design)
- 9+ years of experience in IP Design
- 9+ years of experience Lock, Reset, Power and Scripting
- 7+ years of SoC Design Process
RTL Design Engineer Job Description
- Developing and recommending better design methods/practices to enable better synthesis convergence
- Performing all aspects of design flow from logic synthesis, place and route, FEV, power, timing, quality checks
- Contractor will run testcases on Perf model and RTL verilog simulation and compare metrics of bandwidth and latency
- Contractor will perform debug of perf model and RTL verilog for outlier cases
- Scoping effort, resources, and development schedules for change requests
- Project planning, creating and maintaining schedules, managing dependencies, and ensuring quality of deliverables at committed milestones
- The successful candidate will be a hands-on RTL designer responsible for performing micro-architecture and logic design in high speed IO subsystem for Server processors
- The design goals are balance of high-performance, low latency and power optimizations
- Work with the verification engineers to help on the verification strategies and participate in test plan and coverage reviews
- Close interaction with Physical Design designers in implementation planning and meeting frequency targets
- Knowledge of Verilog and/or VHDL
- BSEE/MSEE with minimum 5 years industry experience
- Mimo, ofdm, agc, channel estimation, ldpc , concepts
- Experience with advanced technology nodes required (28nm, 20 nm, 16 nm)
- Experience in top level timing closure using Synopsys tool flow is highly preferred
- Must have gone through at least one tape-out of a large, high speed design (50 M instances)
RTL Design Engineer Job Description
- Develops, coordinates and conducts Analog and Digital designs and evaluations of engineering design concepts
- Experience creating test plans and procedures for a variety of circuit card and environmental testing
- Develops specifications and requirements, reviews Engineering Change Proposals, and generates formal whitepapers and failure reports
- Oversees or participates in hardware and integration in a laboratory environment testing
- Supports program Engineering Configuration Change Board (CCB), Corrective Action Board (CAB) and Failure Review Boards (FRB), as required
- Identifies opportunities for improvement based on review of failure data and supports development and implementation of component design improvements or updates
- Supports design reviews and test activities, as needed
- Micro-architecture specification development and design
- Working closely with validation, and implementation teams to meet all functional requirements, performance, power and area goals
- Develop and maintain tool flows required for handoff of RTL to SOC teams
- Knowledge & experience of Microarchitecrure, RTL, Synthesis, STA
- For Logic design, experience with Logic Synthesis, Linting, CDC and DFT tools is preferred
- Design and analysis of hardware and software graphics pipelines
- Performance and power measurement and analysis
- Strong scripting skills, with Perl, Python
- Minimum of Masters + 10 years’ experience in DFT
RTL Design Engineer Job Description
- Exercises solid analytical problem solving and troubleshooting skills (e.g., LEC debugging, Functional simulation debugging, Script debugging )
- Model the power profile of a design and use power reduction techniques on the design
- Run LEC on synthesized designs at several places in the design cycle, Pre DFT,Post DFT, Post Layout, ECO
- Coordinate with tool vendors to resolve tool issues, make test cases to show issue
- Mentor less experienced design engineers in implementation tasks to ensure compliance to specification, quality standards, and milestones
- Contractor will work with model developers or RTL designers for appropriate fixes to align outlier casesSearch Jobs US
- Technical leadership of FPGA designs
- Providing guidance to junior engineers
- You will be a key technical contributor on a team enabling high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs
- Work with cross-functional teams and develop micro-architecture, and design SystemVerilog RTL to meet size & timing specifications
- Must be able to meet the test coverage goals and hand off STIL files to the test team
- Should be familiar with ATE equipment and techniques
- Should be familiar with JTag techniques
- Must have knowledge of DFT techniques
- Should have experience of Tetramax ATPG tools from Synopsys
- Should have experience of VCS simulations and be able to perform pattern verification tasks